MG115P arrays equivalent, 0.25m sea of gates and customer structured arrays.
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* 0.25µm drawn 3-, 4-, and 5-layer metal CMOS Optimized 2.5-V core Optimized 3-V I/O SOG and CSA architecture availability 77-ps typical gate .
nsistors and replace them with diffused memory macrocells to the customer’s specifications.
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Oki Semiconductor
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